![]() The D FlipFlop can be interpreted as a delay line or zero order hold. That's why, it is commonly known as a delay flip flop. ![]() The working of D flip flop is similar to the D latch except that the output of D Flip Flop takes the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low) and delays it by one clock cycle. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch.įrom the timing diagram it is clear that the output Q's waveform resembles that of input D's waveform when the clock is high whereas when the clock is low Q retains the previous value of D (the value before clock dropped down to 0) If the data on the D line changes state while the clock pulse is high, then the output, Q, follows the input, D. The D latch is used to capture, or 'latch' the logic level which is present on the Data line when the clock input is high. Latch is an electronic device that can be used to store one bit of information.
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